`timescale 1ns/1ps
//                   DUT   
module counter (
    input  logic       clk,    //       
    input  logic       rst_n,  //                            
    input  logic       en,     //             
    output logic [3:0] cnt,    //             4      
    output logic       ovf     //                         15            
);

always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt <= 4'h0;
        ovf <= 1'b0;
    end else if (en) begin
        if (cnt == 4'hF) begin
            cnt <= 4'h0;
            ovf <= 1'b1;
        end else begin
            cnt <= cnt + 1;
            ovf <= 1'b0;
        end
    end
end

endmodule